7. APPENDIX
LPT Port (Line Printer Port)Logical device name reserved by DOS for the computer parallel ports. Each LPT port is configured to use a different IRQ and address assignment.
MMXA set of 57 new instructions based on a technique called Single Instruction, Multiple Data (SIMD), which is built into the new Intel Pentium PP/MT (P55C) and Pentium
II(Klamath) CPU as well as other
The OnNow design initiative is a comprehensive,
SDRAM is Intel's goal is to ensure that memory subsystems continue to support evolving platform requirements and to assure that memory does not become a bottleneck to system performance. It is especially important to ensure that the PC memory roadmap evolves together with the performance roadmaps for the processors, I/O and graphics.
PCI Bus (Peripheral Component Interconnect Local Bus)PCI bus is a specification that defines a
The PCI Bus Master can perform data transfer without local CPU help and further- more, the CPU can be treated as one of the Bus Masters. PCI 2.1 supports concurrent PCI operation to allow the local CPU and bus master to work simultaneously.
Plug and Play BIOSThe ISA bus architecture requires the allocation of memory and I/O address, DMA channels and interrupt levels among multiple ISA cards. However, configuration of ISA cards is typically done with jumpers that change the decode maps for memory and I/O space and steer the DMA and interrupt signals to different pins on the bus. Further, system configuration files may need to be updated to reflect these changes. Users typically resolve sharing conflicts by referring to documentation provided by each manufacturer. For the average user, this configuration process can be unreliable and frustrating. Plug and play (PnP) BIOS eliminates the ISA
When you turn ON the computer, it will first run through the POST, a series of
PS/2 ports are based on IBM Micro Channel Architecture. This type of architecture transfers data through a
Developed by Rambus, Inc., this type of memory can deliver up to 1.6GB of data per second. RDRAM is the first interface standard that can be directly implemented on high performance VLSI components such as, CMOS DRAMs, memory control-
lers, and graphics/video ICs.ASUS | 101 |
7 . APPENDIX
Glossary