Cypress CY62167E MoBL CY62167E MoBL

CY62167E MoBL®

Switching Waveforms (continued)

tHD

tSD

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZOE

VALID DATA

tBW

NOTE 23

CE1

ADDRESS

CE2

DATA IO

BHE/BLE

Notes

21.Data IO is high impedance if OE = VIH.

22.If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.

23.During this period the IOs are in output state and input signals must not be applied.

[+] Feedback [+] Feedback [+] Feedback

Contents

Main 16-Mbit (1M x 16 / 2M x 8) Static RAM CY62167E MoBL Features Functional Description Logic Block Diagram CY62167E MoBL Document #: 001-15607 Rev. *A Page 2 of 12 Pin Configuration 48-Pin TSOP I Product Portfolio Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Data Retention Characteristics Data Retention Waveform Switching Characteristics CY62167E MoBL Document #: 001-15607 Rev. *A Page 6 of 12 Switching Waveforms Figure 2 shows OE controlled read cycle waveforms.[19, 20] Figure 2. Read Cycle No. 2 CY62167E MoBL Document #: 001-15607 Rev. *A Page 7 of 12 Figure 3 shows WE controlled write cycle waveforms.[17, 21, 22] Figure 3. Write Cycle No. 1 Figure 4 shows CE1 or CE2 controlled write cycle waveforms.[17, 21, 22] Figure 4. Write Cycle No. 2 Figure 5 shows WE controlled, OE LOW write cycle waveforms.[22] Figure 5. Write Cycle No. 3 t Figure 6 shows BHE/BLE controlled, OE LOW write cycle waveforms.[22] Figure 6. Write Cycle No. 4 Truth Table Ordering Information Package Diagram Figure 7. 48-Pin TSOP I (12 mm x 18.4 mm x 1.0 mm), 51-85183 Document History Page