CY7C1357C

CY7C1355C

CY7C1357C

Pin Configurations (continued)

100-Pin TQFP Pinout

BYTE B

VDDQ

VSS

DQB

VSS

VDDQ

DQB DQB

Vss/DNU

VDD

VSS

DQB

VDDQ

VSS

DQB

DQPB

VSS

VDDQ

A		A		CE	CE		NC		NC	BW	BW		CE	V		V		CLK		WE	CEN	OE		ADV/LD		NC/18M		A		A	A
A		A		CE	CE		NC		NC	BW	BW		CE	V		V		CLK		WE	CEN	OE		ADV/LD		NC/18M		A		A	A
				1	2					B	A	3			DD		SS
															DD		SS



100		99		98	97		96		95	94	93	92		91		90		89		88	87	86	85			84		83		82	81
1																															80
2																															79
3																															78
4																															77
5																															76
6																															75
7																															74
8																															73
9																															72
10																															71
11																															70
12																															69
13												CY7C1357C																			68
14												CY7C1357C																			67
14																															67
15																															66
16																															65
17																															64
18																															63
19																															62
20																															61
21																															60
22																															59
23																															58
24																															57
25																															56
26																															55
27																															54
28																															53
29																															52
30																															51
31		32		33	34		35		36	37	38	39		40		41		42		43	44	45	46			47		48		49	50


	MODE		A	A		A		A	A1	A0	NC/288M		NC/144M		SS		DD		NC/72M	NC/36M	A	A			A		A		A	A		A
	MODE		A	A		A		A	A1	A0	NC/288M		NC/144M		V		V		NC/72M	NC/36M	A	A			A		A		A	A		A

VDDQ

VSS

NC DQPA

DQA DQA

VSS

VDDQ

DQA DQA

VSS

VDD

DQA DQA

VDDQ

VSS

DQA DQA NC

VSS

VDDQ

BYTE A

Document #: 38-05539 Rev. *E

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Contents

Features Functional Description1Selection Guide 133 MHz 100 MHz Unit Logic Block Diagram CY7C1355C 256K x Logic Block Diagram CY7C1357C 512K x Pin Configurations Pin Tqfp Pinout CY7C1355C CY7C1357C Pin Configurations Ball BGA Pinout 3 Chip Enables with Jtag CE2 CLK Pin Configurations Ball Fbga Pinout 3 Chip enable with JtagCE2 Power supply inputs to the core of the device Power supply for the I/O circuitryPin Definitions Name Description Single Read Accesses Burst Read AccessesSingle Write Accesses Functional Overview Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Sleep Mode Partial Truth Table for Read/Write2, 3Truth Table for Read/Write2, 3,9 Function CY7C1355C TAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag Bypass Register TAP Instruction Set TAP Timing Parameter Description Min Max Unit ClockOutput Times Set-up Times 3V TAP AC Test Conditions 5V TAP AC Test Conditions5V TAP AC Output Load Equivalent Identification Register Definitions Scan Register Sizes Identification CodesRegister Name Bit Size Instruction Code Description CY7C1355C 256K x Bit# Ball ID Signal CY7C1357C 512K x Bit# Ball Id Signal NameBall BGA Boundary Scan Order Name Ball Fbga Boundary Scan Order CY7C1355C 256K x Bit# Ball ID Signal NameBWD Electrical Characteristics Over the Operating Range13 Maximum RatingsOperating Range Ambient Range Capacitance15 Thermal Resistance15AC Test Loads and Waveforms 3V I/O Test Load Switching Characteristics Over the Operating Range 16 100 Parameter Description Unit Min Max Switching Waveforms CommandRead/Write Waveforms22, 23 Write NOP, Stall and Deselect Cycles22, 23 QA4+1 DA5 QA6 DA7 ZZ Mode Timing26 Ordering Information Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Ball BGA 14 x 22 x 2.4 mm 90±0.05 Soldernotespad Type NON-SOLDER Mask Defined Nsmd Issue Date Orig. Description of Change Document History

Cypress CY7C1355C manual CY7C1357C

Models: CY7C1355C CY7C1357C

Pin Configurations (continued)