2.3.2.6 DMA Controller

Data from the host computer is received automatically by the STB signal via the external Centronics
interface. The data is input to the input buffer on the DRAM (IC5). At this time, E05A96 detects the
rising edgeof the external STB signal and outputs the STBDMA (strobe DMA request) signal to the
CPU. When the CPU detects this signal, the DMA controller in the CPU sends a bus request to the
bus controller in the CPU, and then the CPU releases the bus line. Due to this, external data is
transportedinto the memory, bypassing the CPU.
BACDMAC
BAREQ
E05A96 (IC2)
STB
STBDMA
CPU H8 (IC1)
ACK
BUSY
DREQ1
9129
DMARQ
128 14 DREQ2
166
161
162
Memory
Figure 2-26. DMA Controller Operation
Operating Principles Stylus Pro XL
2-22 REV.-A