S1F79100Y Series

PACKAGE MARKINGS

The markings on S1F79100Y series device packages Marking locations use the following abbreviations.

Parameter

Code

Description

 

 

 

Output voltage code

B

5 V

 

 

D

3 V

 

 

 

 

Voltage regulator code

P

Positive

 

 

N

Negative

 

 

 

 

Note

The reflow furnace temperature profile requirements must be satisfied during package reflow. Avoid soldering on surface mount package (including SOT89) as it causes a quick temperature change of package and a device damage.

Output voltage code

S1F79100Y

Series

 

 

Voltage regulator code

FUNCTIONAL DESCRIPTIONS

Basic Operation

The S1F79100Y series uses a 3-pin series regulator feedback loop. An operational amplifier compares VREG from the voltage divider formed by R1 and R2, with VREF. The amplifier output adjusts the output transistor gate bias to equalize the voltages and compensate for fluctuations in VI.

GND

VREF

R1

–

+

VREG

R2

VI

 

 

 

 

VO

 

 

 

 

The following equation shows the relationship between VO and VREF.

R1 + R2

VO = — — — — — V REF

R1

Internal Circuits

Reference voltage generator

The offset structure used in all three transistors results in a high breakdown voltage that ensures a stable reference voltage output over a wide range of input voltages.

VSS

Enhancement mode

VREF

Depletion mode

Depletion mode

V1

S1F70000 Series Technical Manual

EPSON

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