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CHAPTER 5 CLOCKS
Notes:
• The initial value for the machine clock setting is main clock (CKSCR: MCS = 1, SCS = 1).
• If both the SCS and MCS bits are “0”, the SCS bit takes precedence, that is, the sub-clock is selected.
•When sub-clock mode is switched to PLL clock mode, set the WS1 and WS0 bits of CKSCR to “10B” or “11B.”
(1) Write "0" to MCS bit
(2) Termination of PLL clock oscillation stabilization wait time & CS1, CS0= 00B& CS2= 0
(3) Termination of PLL clock oscillation stabilization wait time & CS1, CS0= 01B& CS2= 0
(4) Termination of PLL clock oscillation stabilization wait time & CS1, CS0= 10B& CS2= 0
(5) Termination of PLL clock oscillation stabilization wait time & CS1, CS0= 11B& CS2= 0
(6) Termination of PLL clock oscillation stabilization wait time & CS1, CS0= 10B& CS2= 1
(7) Write "1" to MCS bit (include reset)
(8) Synchronous timing of PLL clock and main clock
(9) Write "0" to SCS bit
(10) Synchronous timing of main clock and sub-clock
(11) Write "1" to SCS bit (MCS1)
(12) Termination of main clock oscillation stabilization wait time
(13) Termination of main clock oscillation stabilization wait time & CS1, CS0= 00B& CS2= 0
(14) Termination of main clock oscillation stabilization wait time & CS1, CS0= 01B& CS2= 0
(15) Termination of main clock oscillation stabilization wait time & CS1, CS0= 10B& CS2= 0
(16) Termination of main clock oscillation stabilization wait time & CS1, CS0= 11B& CS2= 0
(17) Termination of main clock oscillation stabilization wait time & CS1, CS0= 10B& CS2= 1
(18) Write "1" to SCS bit (MCS0)
(19) Synchronous timing of PLL clock and sub-clock
MCS : Machine clock select bit of clock selection register (CKSCR)
MCM : Machine clock display bit of clock selection register (CKSCR)
SCS : Machine clock display bit (sub) of clock selection register (CKSCR)
SCM : Machine clock select bit (sub) of clock selection register (CKSCR)
CS1, CS0 : Machine clock of clock selection register (CKSCR)
CS2 : Multiplication rate selection bit of PLL/ subclock control register (PSCCR)