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CHAPTER 16 8-/16-BIT PPG TIMER
16.3.3 PPGC/D Count Clock Select Register (PPGCD)
The PPGC/D count clock select register selects the count clock of the 8-/16-bit PPG
timers C and D and the output pin.
This section explains the PPGCD function only. The PPGEF has the same function as
the PPGCD, and the 8-/16-bit PPG timers E and F are set.
■PPGC/D Count Clock Select Register (PPGCD)
Figure 16.3-4 PPGC/D Count Clock Select Register (PPGCD)
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76
−R/WR/WR/WR/WR/W
R/W
HCLK
φ
R/W
X
−
0
0
0
0
0
0
X
0
B
R/W
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 REV
Address:
chD PPGCD 00004AH
Other channel:
chF PPGEF 00004EH
: Read/Write
: Indeterminate
: Undefined
: Reset value
: Oscillation clock
: Machine clock frequency
bit 0
REV PPG output pin select bit
0Output pulse from standard output pin
1Switch output pin between PPGn and PPGm
Reset value
bit 7bit 6bit 5
PCS2 PCS1 PCS0 PPGD
count clock select bits
0 0 0 1/φ(41.7 ns)
0012/φ(83.3 ns)
010
22/φ(167 ns)
011
23/φ(333 ns)
100
24/φ(667 ns)
101
Setting disable
110
Setting disable
111
29/HCLK(128 µs)
bit 4 bit 3 bit 2
PCM2 PCM1 PCM0 PPGC
count clock select bits
0001/φ(41.7 ns)
0012/φ(83.3 ns)
010
22/φ(167 ns)
011
23/φ(333 ns)
100
24/φ(667 ns)
101
Setting disable
110
Setting disable
111
29/HCLK(128 µs)
The parenthesized values are provided when the oscillation c lock oper ate s at
4 MHz and the machine clock operates at 24 MHz.
n = C, E
m = n+1