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21.4.22 Acceptance Mask Registers 0 and 1 (AMR0 and AMR1)
There are two acceptance mask registers, which are available either in the standard
frame format or extended frame format.
AM28 to AM18 (11 bits) are used for acceptance masks in the standard fram e f orma t and
AM28 to AM0 (29 bits) are used for acceptance masks in the extended format.
■Register Configuration
Figure 21.4-22 Configuration of the Acceptance Mask Register 0 (AMR0)
Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 AMR01(Byte0)
CAN1: 007D14HAM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21 Reset value
XXXXXXXXB
R/WR/WR/WR/WR/WR/WR/WR/W
Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 AMR01(Byte1)
CAN1: 007D15HAM20 AM19 AM18 AM17 AM16 AM15 AM14 AM13 Reset value
XXXXXXXXB
R/WR/WR/WR/WR/WR/WR/WR/W
Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 AMR01(Byte2)
CAN1: 007D16HAM12 AM11 AM10 AM9 AM8 AM7 AM6 AM5 Reset value
XXXXXXXXB
R/WR/WR/WR/WR/WR/WR/WR/W
Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 AMR01(Byte3)
CAN1: 007D17HAM4 AM3 AM2 AM1 AM0 −−−Reset value
XXXXXXXXB
R/W R/W R/W R/W R/W −−−
R/W
X
−
: Read/Write
: Undefined
: Unused
: Used bit in typical frame format