573
APPENDIX A I/O Maps
■I/O map (79XX - 7FXX addresses)
Table A-2 I/O Map (7900H - 7FFFH) (1/3)
Address Register Abbreviation Access Peripheral Initial value
7900H to
7917HReserved
7918HReload register LC PRLLC R/W
16-bit
PPG C/D
XXXXXXXXB
7919HReload register HC PRLHC R/W XXXXXXXXB
791AHReload register LD PRLLD R/W XXXXXXXXB
791BHReload register HD PRLHD R/W XXXXXXXXB
791CHReload register LE PRLLE R/W
16-bit
PPG E/F
XXXXXXXXB
791DHReload register HE PRLHE R/W XXXXXXXXB
791EHReload register LF PRLLF R/W XXXXXXXXB
791FHReload register HF PRLHF R/W XXXXXXXXB
7920HInput capture 0 IPCP0 R
Input Capture 0/1
XXXXXXXXB
7921HInput capture 0 IPCP0 R XXXXXXXXB
7922HInput capture 1 IPCP1 R XXXXXXXXB
7923HInput capture 1 IPCP1 R XXXXXXXXB
7924HInput capture 2 IPCP2 R
Input Capture 2/3
XXXXXXXXB
7925HInput capture 2 IPCP2 R XXXXXXXXB
7926HInput capture 3 IPCP3 R XXXXXXXXB
7927HInput capture 3 IPCP3 R XXXXXXXXB
7928H to
793FHReserved
7940HTimer data 0 TCDT0 R/W
I/O Timer 0
0 0 0 0 0 0 0 0B
7941HTimer data 0 TCDT0 R/W 0 0 0 0 0 0 0 0B
7942HTimer control 0 TCCSL0 R/W 0 0 0 0 0 0 0 0B
7943HTimer control 0 TCCSH0 R/W 0XXXXXXXB
7944H to
794BHReserved
794CHTimer 2/reload 2 TMR2/
TMRLR2
R, W 16-bit Reload
Timer 2
XXXXXXXXB
794DHR, W XXXXXXXXB
794EHTimer 3/reload 3 TMR3/
TMRLR3
R, W 16-bit Reload
Timer 3
XXXXXXXXB
794FHR, W XXXXXXXXB