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APPENDIX
■Write, Data Polling, Read (CE control)
Figure C-3 Timing Diagram for Write Access (CE control)
Note:
• Describes the last 2-bus cycle of 4-bus cycle sequences.
• "Fx" in "FxAAAA" described as address is any of F.
A
Q18 to AQ0
WE
OE
CE
DQ7 to DQ0
tWC
PA
tAS tAH
PA
tWHWH1
tCP
tWS
tCPH
tDH
tDS
A0HPD DQ7
tGHWL
tWH
Dout
FxAAAAH
3rd bus cycle Data polling
PA : Write address
PD : Write data
DQ7 : Reverse output of write data
DOUT : Output of write data