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CHAPTER 3 INTERRUPTS
[bit 15 to bit 12, bit 7 to bit 4] ICS 3 to ICS 0 (extended intelligent I/O se rvice channel select bits)
ICS3 to ICS0 are write-only bits. These bits specify the EI2OS channel. The values set in these bits
determined the extended intelligent I/O service descriptor addresses in memory, which is explained
later. The ICS bits are initialized to "0000B" by a reset.
Table 3.3-2 describes the correspondence between the ICS bits, channel numbers, and descriptor
addresses.
Table 3.3-2 ICS Bits, Channel Numbers, and Descriptor Address
ICS3 ICS2 ICS1 ICS0 Selected channel Descriptor address
0 0 0 0 0 000100H
0 0 0 1 1 000108H
0 0 1 0 2 000110H
0 0 1 1 3 000118H
0 1 0 0 4 000120H
0 1 0 1 5 000128H
0 1 1 0 6 000130H
0 1 1 1 7 000138H
1 0 0 0 8 000140H
1 0 0 1 9 000148H
1 0 1 0 10 000150H
1 0 1 1 11 000158H
1 1 0 0 12 000160H
1 1 0 1 13 000168H
1 1 1 0 14 000170H
1 1 1 1 15 000178H