■Extended Intelligent I/O Service (EI2OS)
•In addition to programming being made
easier, because there in no need to |
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execute unnecessary program transfers |
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higher speeds for transfer service |
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response and overall system control are |
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realized. |
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•Since CPU |
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transfer functions, |
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can be realized at no extra cost. |
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•Since I/O transfers can be stopped when |
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a condition is generated such as when | 4 |
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invalid data is received, performance loss |
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due to transfering unnecessary data can |
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be avoided because there is no |
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programming load. |
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•It is possible to specify incrementing or |
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decrementing of buffer addresses and |
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I/O register addresses can be specified. |
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•It is possible to specify the entire 00 bank |
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as I/O register addresses. |
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•It is possible to specify the data counter |
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to count up to 64K. |
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•Execution speed |
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From request to completion of transfer: |
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28 cycles = 1.75µs (@16 MHz) |
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Memory space |
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I/O registers |
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| Peripheral |
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| I/O register |
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IOA |
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| 2 Interrupt requests | 1 |
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(I/O address) |
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ISD |
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| ICS |
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| Interrupt controller |
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BAP |
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| Interrupt control register |
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(Memory address) |
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| Operation mechanism |
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| 1. An I/O transfer request is generated. | ||||||||||
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| 2. The interrupt controller selects a descriptor. | ||||||||||
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| 3.Transfer source and destination addresses | ||||||||||
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| are read out of the descriptor. |
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Memory |
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| ory space. |
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| I/O |
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| Memory | |||||||
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(000000H to 00FFFFH) |
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