32-bit FR Family

■FR Family Features

•CPU core capable of running at a peak rate of 64 VAX MIPS (CPU core performance) at 50 MHz while featuring its compactness equivalent to 16-bit microcontrollers

•5-stage pipelining and harvard-bus architecture, allowing efficient execution

•Implementation of, basically, 16-bit fixed length commands, providing high object code efficiency

•The command group enhanced for controllers and an algorithm engine, resulting in faster execution of instruc- tions

•A variety of resources including the sum-of-product units

•Many kinds of internal peripheral devices

•FR architecture features

High-speed

Fast interrupt

Real time processing

processing

processing

 

 

 

Algorithm engine

I/O operation

High coding efficiency

Fixed-length instructions

RISC CPU features

•5-stage pipelining

•1 instruction/cycle

•Load/store

result in a compact CPU core.

60,000 transistors (including a multiplier & barrel shifter)

Efficient

development

Support for high-level languages

Special (high-speed) processing

Assembler coding

•Fujitsu embedded RISC controller

The FR family is designed for optimum use in control systems while the SPARClite is suitable for data processing systems.

Performance

Performance

 

 

 

FR-V family

 

 

FR-Next

 

 

 

 

 

 

Improvement in a bus

 

FR family

 

function

 

 

 

 

 

 

FR60 (66 MHz)

 

F2MC-16LX family

 

 

 

 

 

F2MC-8L family

 

FR30

FR60Lite (33 MHz)

 

 

 

 

 

 

 

 

Low power

 

 

 

 

 

 

F2MC: Single chip 8 to 16-bit microcontrollers

 

 

FR: Single chip-oriented (32-bit) RISC machines

 

 

SPARClite: Oriented for performance-focused open software

 

 

 

 

 

 

 

 

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