IBM 520Q, P5 520

Chapter 2. Architecture and technical overview 27

򐂰Double the SMP support. Changes have been made in the fabric, L2 and L3 controller,

memory controller, GX controller, and processor RAS to provide support for the QCM that

allows the SMP system sizes to be double that which is available in POWER5 DCM-based

servers. However, current POWER5+ implementations only support single address loop.

򐂰Several enhancements have been made in the memory controller for improved

performance. The memory controller is ready to support DDR2 667 MHz DIMMs in the

future.

򐂰Enhanced redundancy in L1 cache, L2 cache, and L3 directory. Independent control of the

L2 cache and the L3 directory for redundancy to allow split-repair action has been added.

More word line redundancy has been added in the L1 Dcache. In addition, Array Built-In

Self Test (ABIST) column repair for the L2 cache and the L3 directory has been added.

2.2 Processor and cache

In the p5-520 and p5-520Q, the POWER5+ processors, associated L3 cache (if present), and

memory DIMMs are packaged on the system planar. The p5-520 1-core, 2-core, and

p5-520Q 4-core systems use different POWER5+ processor modules.

2.2.1 POWER5+ single-core module

The 1-core p5-520 POWER5+ system planar contains a single-core module (SCM) and the

local memory storage subsystem for that SCM. The POWER5+ single-core processor is

packaged in the SCM. The 1-core 1.65 GHz system planar contains a single-core module

(SCM) and the local memory storage subsystem for that SCM. L3 Cache is not available in

this configuration. Figure2-3 on page 27 shows the layout of a 1.65 GHz p5-520 SCM and

associated memory.

Figure 2-3 p5-520 POWER5+ 1.65 SCM with DDR2 memory socket layout view

The 1-core 2.1 GHz p5-520 system planar contains a single-core module (SCM), the local

memory storage subsystem for that SCM, and the L3 Cache. Figure2-4 shows the layout of a

2.1 GHz p5-520 SCM and associated memory.

Note: Because the POWER5+ processor modules are soldered directly to the system

planar, you must take special care in sizing and selecting the ideal CPU configuration.

POWER5+

core

1.9 MB Shared

L2 cache

Ctrl

Mem

Ctrl

Single-Core Module

SCM

SMI-II SMI-II

1056 MHz

2 x 8 B for read

2 x 2 B for write

DIMM

2 x 8 B

@528 MHz

GX+

Ctrl

Enhanced distributed switch

GX+

Bus

POWER5+

core

POWER5+

core

1.9 MB Shared

L2 cache

Ctrl

Mem

Ctrl

Single-Core Module

SCM

SMI-II SMI-II

1056 MHz

2 x 8 B for read

2 x 2 B for write

DIMM

2 x 8 B

@528 MHz

GX+

Ctrl

Enhanced distributed switch

GX+

Bus