User’s Manual
Preliminary PPC440x5 CPU Core
ppc440x5LOT.fm.
September 12, 2002 Page 19 of 583
Tables
Table 2-1. Data Operand Definitions .......................................................................................................40
Table 2-2. Alignment Effects for Storage Access Instructions ................................................................40
Table 2-3. Register Categories ...............................................................................................................50
Table 2-4. Instruction Categories ............................................................................................................ 57
Table 2-5. Integer Storage Access Instructions ......................................................................................58
Table 2-6. Integer Arithmetic Instructions ................................................................................................58
Table 2-7. Integer Logical Instructions .................................................................................................... 59
Table 2-8. Integer Compare Instructions .................................................................................................59
Table 2-9. Integer Trap Instructions ....................................................................................................... 59
Table 2-10. Integer Rotate Instructions ..................................................................................................... 59
Table 2-11. Integer Shift Instructions ........................................................................................................60
Table 2-12. Integer Select Instruction .......................................................................................................60
Table 2-13. Branch Instructions ................................................................................................................60
Table 2-14. Condition Register Logical Instructions ..................................................................................61
Table 2-15. Register Management Instructions ........................................................................................61
Table 2-16. System Linkage Instructions .................................................................................................. 61
Table 2-17. Processor Synchronization Instruction ...................................................................................62
Table 2-18. Cache Management Instructions ...........................................................................................62
Table 2-19. TLB Management Instructions ............................................................................................... 62
Table 2-20. Storage Synchronization Instructions .....................................................................................63
Table 2-21. Allocated Instructions ............................................................................................................. 63
Table 2-22. BO Field Definition ................................................................................................................. 65
Table 2-23. BO Field Examples ................................................................................................................65
Table 2-24. CR Updating Instructions ....................................................................................................... 69
Table 2-25. XER[SO,OV] Updating Instructions ........................................................................................73
Table 2-26. XER[CA] Updating Instructions .............................................................................................. 73
Table 2-27. Privileged Instructions ............................................................................................................ 80
Table 3-1. Reset Values of Registers and Other PPC440x5 Facilities ...................................................86
Table 4-1. Instruction and Data Cache Array Organization .....................................................................96
Table 4-2. Cache Sizes and Parameters ................................................................................................96
Table 4-3. Victim Index Field Selection ................................................................................................... 98
Table 4-4. Icread and dcread Cache Line Selection ............................................................................. 112
Table 4-5. Data Cache Behavior on Store Accesses ............................................................................ 121
Table 5-1. TLB Entry Fields ...................................................................................................................135
Table 5-2. Page Size and Effective Address to EPN Comparison ........................................................ 140
Table 5-3. Page Size and Real Address Formation .............................................................................. 142