srawi
Shift Right Algebraic Word Immediate
Preliminary PPC440x5 CPU Core User’s Manual
instrset.fm.
September 12, 2002 Page 407 of 589
srawi
Shift Right Algebraic Word Immediate
n←SH
r←ROTL((RS), 32 – n)
m←MASK(n, 31)
s←(RS)0
(RA) ←(r ∧m) ∨(32s∧¬m)
XER[CA] ←s∧((r ∧¬m)≠0)
The contents of register RS are shifted right by the number of bits specified in the SH field. Bits shifted out of
the least significant bit are lost. Bit RS0 is replicated to fill the vacated positions on the left. The result is
placed into register RA.
If register RS contains a negative number and any 1-bits were shifted out of the least significant bit position,
XER[CA] is set to 1; otherwise, it is set to 0.
Registers Altered
•RA
• XER[CA]
• CR[CR0] if Rc contains 1
srawi RA, RS, SH Rc=0
srawi. RA, RS, SH Rc=1
31 RS RA SH 824 Rc
0 6 11 16 21 31