IBM PPC440X5 - page 479

DCDBTRL
Data Cache Debug Tag Register Low
Preliminary PPC440x5 CPU Core User’s Manual
regsumm440core.fm.
September 12, 2002 Page 479 of 589
DCDBTRL
SPR 0x39C Supervisor Read-Only
See dcread Operation on page 127.
Figure 10-14. Data Cache Debug Tag Register Low (DCDBTRL)
0:12 Reserved
13 UPAR U bit parity The parity for the U0-U3 bits in the cache line read
bydcread if CCR0[CRPE] = 1, otherwise 0.
14:15 TPAR Tag parity The parity for the tag bits in the cache line read by
dcread if CCR0[CRPE] = 1, otherwise 0.
16:19 DPAR Data parity The paritycheck values for the data bytes in the word read bydcread if CCR0[CRPE] = 1, other-
wise 0.
20:23 MPAR Modified (dirty) parity The parity for the modified (dirty) indicators for eachof the four doublewords in the cache line read
bydcread if CCR0[CRPE] = 1, otherwise 0.
24:27 D Dirty Indicators The“dirty” (modified) indicators for each of the four
doublewords in the cache line read bydcread.
28 U0 U0 Storage Attribute The U0 storage attribute for the memory page
associated with this cache line read bydcread.
29 U1 U1 Storage Attribute The U1 storage attribute for the memory page
associated with this cache line read bydcread.
30 U2 U2 Storage Attribute The U2 storage attribute for the memory page
associated with this cache line read bydcread.
31 U3 U3 Storage Attribute The U3 storage attribute for the memory page
associated with this cache line read bydcread.
0 12 13 14 15 16 19 20 23 24 27 28 29 30 31
D
U0
U1 U3
U2
UPAR
TPAR
DPAR
MPAR