User’s Manual
PPC440x5 CPU Core Preliminary
Page 554 of 589 instalfa.fm.
September 12, 2002
tlbsync
tlbsyncdoes not complete until all previous TLB-update instruc-
tions executed by this processor have been received and com-
pleted by all other processors.
For the PPC440x5 core,tlbsync is a no-op.
438
tlbwe RS, RA,WS
tlbentry←TLB[(RA)26:31]
if WS = 0
tlbentry[EPN,V,TS,SIZE]←(RS)0:27
tlbentry[TID]←MMUCR[STID]
else if WS = 1
tlbentry[RPN]←(RS)0:21
tlbentry[ERPN]←(RS)28:31
else if WS = 2
tlbentry[U0,U1,U2,U3,W,I,M,G,E]←(RS)16:24
tlbentry[UX,UW,UR,SX,SW,SR]←(RS)26:31
else tlbentry←undefined
439
TableA-1. PPC440x5 Instruction Syntax Summary (continued)
Mnemonic Operands Function Other Registers
Changed Page