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| Signal Group | Type | Signals |
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| Single ended | CMOS Output | SM_DRAMRST# |
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| DDR3/DDR3L Data Signals 2 |
| |
| Single ended | DDR3/DDR3L Bi- | SA_DQ[63:0], SB_DQ[63:0] |
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| directional |
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| Differential | DDR3/DDR3L Bi- | SA_DQSP[7:0], SA_DQSN[7:0], SB_DQSP[7:0], SB_DQSN[7:0] |
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| directional |
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| DDR3/DDR3L Reference Voltage Signals | ||
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| DDR3/DDR3L | SM_VREF, SA_DIMM_VREFDQ, SB_DIMM_VREFDQ |
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| Output |
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| Testability (ITP/XDP) |
| |
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| Single ended | CMOS Input | TCK, TDI, TMS, TRST# |
|
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| Single ended | GTL | TDO |
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| Single ended | Output | DBR# |
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| Single ended | GTL | BPM#[7:0] |
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| Single ended | GTL | PREQ# |
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| Single ended | GTL | PRDY# |
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| Control Sideband |
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| Single ended | GTL Input/Open | PROCHOT# |
|
| Drain Output |
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|
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| Single ended | Asynchronous | THERMTRIP#, IVR_ERROR |
|
| CMOS Output |
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| Single ended | GTL | CATERR# |
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| Single ended | Asynchronous | PM_SYNC,RESET#, PWRGOOD, PWR_DEBUG# |
|
| CMOS Input |
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| Single ended | Asynchronous Bi- | PECI |
|
| directional |
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|
|
|
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| Single ended | GTL | CFG[19:0] |
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|
|
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| Single ended | Analog Input | SM_RCOMP[2:0] |
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|
|
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| Voltage Regulator |
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|
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| Single ended | CMOS Input | VR_READY |
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| Single ended | CMOS Input | VIDALERT# |
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| Single ended | Open Drain Output | VIDSCLK |
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|
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| Single ended | GTL Input/Open | VIDSOUT |
|
| Drain Output |
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| Differential | Analog Output | VCC_SENSE, VSS_SENSE |
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| Power / Ground / Other |
| |
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| Single ended | Power | VCC, VDDQ |
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| Ground | VSS, VSS_NCTF 3 |
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| No Connect | RSVD, RSVD_NCTF |
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| Test Point | RSVD_TP |
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| continued... |
Intel® Xeon® Processor |
| ||
Datasheet – Volume 1 of 2 |
| June 2013 | |
92 |
|
| Order No.: |