©
National Instruments Corporation 3-1 PCI-6110E/6111E User Manual
Chapter
3
Hardware Overview

This chapter presents an overview of the hardware functions on your

611X E board. Figure 3-1 shows a block diagram for the

PCI-6110E board.

Figure 3-1. PCI-6110E Block Diagram
Timing
PFI / Trigger

I/O Connector

RTSI Bus

PCI Bus

Digital I/O (8)
EEPROM
+
CH0
Amplifier
–
Calibration
Mux
AI CH0
Mux CH0
Latch
Analog
Trigger
Circuitry
2
Trigger Level
DACs
Trigger
12
4Calibration
DACs
DAC0
DAC1
CH0
12-Bit ADC
DAQ - STC
Analog Input
Timing/Control
Analog Output
Timing/Control
Digital I/O
Trigger
Counter/
Timing I/O
RTSI Bus
Interface
DMA/IRQ
Bus
Interface
DAC
FIFO Data (32)
Address/Data
Control
Data (32)
Analog
Input
Control
EEPROM
Control DMA
Interface
FPGA
DAQ-STC
Bus
Interface
Analog
Output
Control
I/O
Bus
Interface
Mini
MITE
Generic
Bus
Interface
PCI
Bus
Interface
IRQDMA
AO Control
CH0+
CH0-
+
CH1
Amplifier
–
AI CH1
Mux CH1
Latch
12
CH1
12-Bit ADC
CH1+
CH1-
+
CH2
Amplifier
–
AI CH2
Mux CH2
Latch
12
CH2
12-Bit ADC
CH2+
CH2-
+
CH3
Amplifier
–
AI CH3
Mux CH3
Latch
12
CH3
12-Bit ADC
CH3+
CH3-
AI Control
Data (16)
Data (16)
Data (16)
Data (16)
ADC
FIFO
Data (16)
PCI_E.book Page 1 Thursday, June 25, 1998 12:55 PM