NEC 78K/0 Series - page 45

45

CHAPTER 4 INSTRUCTION SET

User's Manual U12326EJ4V0UM

Unconditional

BR !addr16 1001 1011 Low addr High addr

Branch $addr16 1111 1010 jdisp

AX 0011 0001 1001 1000

Conditional BC $addr16 1000 1101 jdisp

Branch BNC $addr16 1001 1101 jdisp

BZ $addr16 1010 1101 jdisp

BNZ $addr16 1011 1101 jdisp

BT saddr.bit,$addr16 1

B2B1B0

1100 Saddr-offset jdisp

sfr.bit,$addr16 0011 0001 0

B2B1B0

0110 Sfr-offset jdisp

A.bit,$addr16 0011 0001 0

B2B1B0

1110 jdisp

PSW.bit,$addr16 1

B2B1B0

1100 0001 1110 jdisp

[HL].bit,$addr16 0011 0001 1

B2B1B0

0110 jdisp

BF saddr.bit,$addr16 0011 0001 0

B2B1B0

0011 Saddr-offset jdisp

sfr.bit,$addr16 0011 0001 0

B2B1B0

0111 Sfr-offset jdisp

A.bit,$addr16 0011 0001 0

B2B1B0

1111 jdisp

PSW.bit,$addr16 0011 0001 0

B2B1B0

0011 0001 1110 jdisp

[HL].bit,$addr16 0011 0001 1

B2B1B0

0111 jdisp

BTCLR saddr.bit,$addr16 0011 0001 0

B2B1B0

0001 Saddr-offset jdisp

sfr.bit,$addr16 0011 0001 0

B2B1B0

0101 Sfr-offset jdisp

A.bit,$addr16 0011 0001 0

B2B1B0

1101 jdisp

PSW.bit,$addr16 0011 0001 0

B2B1B0

0001 0001 1110 jdisp

[HL].bit,$addr16 0011 0001 1

B2B1B0

0101 jdisp

DBNZ B,$addr16 1000 1011 jdisp

C,$addr16 1000 1010 jdisp

saddr,$addr16 0000 0100 Saddr-offset jdisp

CPU SEL RBn 0110 0001 11

RB1

1

RB0

000

control NOP 0000 0000

EI 0111 1010 0001 1110

DI 0111 1011 0001 1110

HALT 0111 0001 0001 0000

STOP 0111 0001 0000 0000

Instruction

Mnemonic

Operands Operation Code

Group B1 B2 B3 B4

Contents

Main Page IEBus is a trademark of NEC Corporation. NOTES FOR CMOS DEVICES 4 Regional Information NEC Electronics Hong Kong Ltd. Device availability Ordering information Product release schedule Page INTRODUCTION Page Page Page Page Page 1.7 Special Function Register (SFR) Area 1.8 External Memory Space 1.9 IEBusTM Register Area 14 CHAPTER 2 REGISTERS 2.1 Control Registers Page Figure 2-5. Data to Be Reset from Stack Memory 2.2 General-Purpose Registers CHAPTER 2 REGISTERS Figure 2-6. General-Purpose Register Configuration (a) Absolute names (b) Functional names 2.3 Special Function Registers (SFRs) 20 CHAPTER 3 ADDRESSING 3.1 Instruction Address Addressing Page Page Page 3.2 Operand Address Addressing Page Page Page Page Page Page Page 32 CHAPTER 4 INSTRUCTION SET 4.1 Operation Page Page CHAPTER 4 INSTRUCTION SET Note Except r = A. CHAPTER 4 INSTRUCTION SET Note Only when rp = BC, DE or HL. (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Page 4.2 Instruction Codes 4.2.2 Instruction code list Notes 1. Only when rp = BC, DE or HL. 2. Except r = A. Page Page Page Page Page Page Page Page MOV XCH Page MOVW XCHW Page ADD ADDC SUB SUBC AND OR XOR CMP Page ADDW SUBW CMPW Page MULU DIVUW Page INC DEC INCW DECW Page ROR ROL RORC ROLC ROR4 ROL4 Page ADJBA ADJBS Page MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 Page CALL CALLF CALLT BRK RET RETI RETB Page PUSH POP MOVW SP , src MOVW AX, SP Page BR Page BC BNC BZ BNZ BT BF BTCLR DBNZ Page SEL RBn NOP EI DI HALT STOP APPENDIX A REVISION HISTORY 124 APPENDIX B INSTRUCTION INDEX (MNEMONIC: BY FUNCTION) Page 126 APPENDIX C INSTRUCTION INDEX (MNEMONIC: IN ALPHABETICAL ORDER) Page Page Facsimile Message Thank you for your kind support. From: