21
µ
PD17062
Fig. 2-2 Operation of Branch Instruction and Machine Code
(a) Direct branch (BR addr) (b) Indirect branch (BR @AR)
Address Program memory
Label: Instruction (Machine code)
Page 0
Page 1
0000H
0500H
07FFH
0800H
0900H
0F7FH
BR AAA (0C500)
BR BBB (0D100)
AAA:
BBB:
BR AAA (0C500)
BR BBB (0D100)
Address Program memory
Label: Instruction (Machine code)
Page 0
Page 1
0000H
0010H
0085H
0500H
07FFH
0800H
0F7FH
MOV AR0, #5H
MOV AR1, #8H
BR
@AR
MOV AR0, #0H
MOV AR1, #1H
BR
@AR
Remark The machine code (16 bits) of the 17K series consists of five blocks, of one bit, four bits, three bits,
four bits, and four bits. In this document, machine code is represented in these blocks so that
it can be easily understood.
Example Machine code 0C500 →0 1100 101 0000 0000
14 3 4 4
2.4.3 Notes on Debugging
Direct branch instructions to page 0 (addresses 0000H to 07FFH) and page 1 (addresses 0800H to 0F7FH)
use different operation codes, as shown in Fig. 2-2.
The operation codes of the direct branch instructions to page 0 and page 1 are 0CH, and 0DH, respectively.
The difference arises because the direct branch instruction uses the addr operand, which is only 11 bits
long, together with the least significant bit of the operation code, to specify the branch destination address.
When assembling a program, the 17K series assembler (AS17K) references a jump destination identified
by a label and automatically converts the that instruction.
If the program is patched during debugging, the programmer must determine whether the branch
destination is on page 0 or page 1 and convert the instruction into operation code 0CH or 0DH.
If address BBB in (a) of Fig. 2-2 is patched from 0900H to 0910H, for example, the machine code of the BR
BBB instruction must be changed to 0D110.