CHAPTER 6 16-BIT TIMER 20
User’s Manual U15331EJ4V1UD 113
6.4 16-Bit Timer 20 Operation
6.4.1 Operation as timer interrupt
16-bit timer 20 can generate interrupts repeatedly each time the free-running counter value reaches the value set
to CR20. Since this counter is not cleared and holds the count even after an interrupt is generated, the interval time is
equal to one cycle of the count clock set in TCL201 and TCL200.
To operate 16-bit timer 20 as a timer interrupt, the following settings are required.
• Set count values in CR20
• Set 16-bit timer mode control register 20 (TMC20) as shown in Figure 6-4.
Figure 6-4. Settings of 16-Bit Timer Mode Control Register 20 for Timer Interrupt Operation
−0/1 0/1 0/1 0/1 0/1 0/1 0/1
TOD20 TOF20
CPT201 CPT200
TOC20
TCL201 TCL200
TOE20
TMC20
Setting of count clock (see Table 6-2)
Caution If both the CPT201 and CPT200 flags are set to 0, the capture edge operation is prohibited.
When the count value of 16-bit timer counter 20 (TM20) matches the value set in CR20, counting of TM20
continues and an interrupt request signal (INTTM20) is generated.
Table 6-2 shows interval time, and Figure 6-5 shows timing of timer interrupt operation.
Caution When rewriting the value in CR20 during a count operation, be sure to execute the following
processing.
<1> Disable interrupts (set TMMK20 (bit 2 of interrupt mask flag register 1 (MK1)) to 1).
<2> Disable inversion control of timer output data (set TOC20 to 0)
If the value in CR20 is rewritten in the interrupt-enabled state, an interrupt request may occur at
the moment of rewrite.
Table 6-2. Interval Time of 16-Bit Timer 20
TCL201 TCL200 Count Clock Interval Time
0 0 Timer 61 interrupt signal Cycle of timer 61 interrupt signal × 216
0 1 1/fX (0.2
µ
s) 216/fX (13.1 ms)
1 0 22/fX (0.8
µ
s) 218/fX (52.4 ms)
1 1 25/fX (6.4
µ
s) 221/fXT (419 ms)
Remarks 1. f
X: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.