CHAPTER 5 CLOCK GENERATOR
User’s Manual U15331EJ4V1UD 97
Figure 5-2. Clock Generator Block Diagram (
µ
PD78F9488, 78F9489)
Subsystem
clock oscillator
f
XT
X1
X2
XT1
XT2
Main system
clock oscillator
f
X
f
X
2
2
f
XTT
2
1/2
Prescaler Clock to peripheral
hardware
Timer 50
Watch timer
LCD controller/driver
CPU clock
(f
CPU
)
Standby
controller Wait
controller
Selector
STOP MCC PCC1 CLS CSS0
Internal bus
Subclock oscillation
mode register (SCKM)
FRC SCC
Internal bus
Subclock control
register (CSS)
Processor clock
control register (PCC)
×
4 multiplication
circuit ×
2 multiplication
circuit
Selector
Subclock selection
register (SSCK)
SCT
f
XTT
8f
XT
Remark fXTT: fXT or 8fXT