Appendix
Appendix-11
Appendix C. Memory Connection Example
Fig. C-1 shows a connection example for the memory configuration described below.
Block 0: 16-bit bus, 4-Mbit ROM (262 144 words x 16 bits)
Block 1: 16-bit bus, 4-Mbit DRAM (262 144 words x 16 bits, 2 CAS control)
Block 2: 8-bit bus, 1-Mbit SRAM (131 072 words x 8 bits)
Fig. C-1 Memory Connection Example
Note : Fig. C-1 is provided as a reference example, and is not intended to guarantee operation.
WE0
MN103001G
/MN1030F01K
RE
A[23:0]
DWE
DCAS[1:0]
RAS1
CS2
D[15:0]
A[17:0]
D[15:0]
CE
OE
4-Mbit ROM
CS0
D[15:0]
A[18:1]
A[8:0]
D[15:0]
RAS
LCAS
OE
WE
4-Mbit DRAM
A[16:0]
D[7:0]
CE
OE
WE
1-Mbit SRAM
UCAS
DCAS[1]
D[15:0]
DCAS[0]
A[16:0]
D[7:0]
A[9:1]
xx4260