Panasonic MN103001G/F01K

Errors

Page Corrections

Page

- vii -

(In the table of Example.)

(The 2nd line from the bottom.)

An oscillation stabilization wait time of at least 14 ms is recommended.

(In fig.12-5-2.)

4.369 ms to 1118.481 ms <Recommended value is 14 ms or longer.>

(Addition of the following note in the description of Bit No.3.)

Note: When P83A of the port 8 analog/digital input control register

P8AD is "1", IRQ7 is treated as "L" internally by the

microcontroller and reading the SC3CTS bit returns a value of

"0", regardless of the actual values of the port pins.

(In page1-3, 13-3, 13-4, 13-14, 13-15, 13-24,

13-36, 13-45, 13-46, 13-47.)

bit rate

(In page1-3, 13-3, 13-4, 13-14, 13-15, 13-24,

13-36, 13-46, 13-47.)

bit/s

• Conversion accuracy 10 bits ±5 LSB (Linearity error)

[Note 2]

When pin Nos. 45 to 48, respectively, are ...

(In the table 16-6-1.)

Flash on-board rewrite control register

(Name of FAREG in the table 16-6-1.)

Flash address register (Lower)

(

Name of FAREGEX in the table 16-6-1.

) Flash address register

(Upper)

(In the table 16-6-1.) Flash on-board rewrite enable register

(From the 3rd line of [Ordering method 1].)

... for the user non-maskable interrupt processing routine. This is not

necessary if non-maskable interrupts are not being used, however.)

(The 4th line of [Ordering method 2].)

...when a non-maskable interrupt ...

(The 6th line of [Ordering method 2].)

... of the user non-maskable interrupt processing routine ...

(The 8th line of [Ordering method 2].)

If the user is not using non-maskable interrupt processing, ...

(In the fig.17-2-2.) the non-maskable interrupt processing routine

(In addition to these corrections, how to describe the unit is changed ,

but the data are not changed.

Example) P.12-2, 2nd line of "12.2 Features"

Error : 8 to 15 MHz Correction : 8 MHz to 18 MHz )

(In the table of Example.)

(The 2nd line from the bottom.)

An oscillation stabilization wait time of at least 17ms is

recommended.

(In fig.12-5-2.)

4.369 ms to 1118.481 ms

(Following words in page1-3, 13-3, 13-4, 13-14, 13-15, 13-24,

13-36, 13-45, 13-46, 13-47.)

transfer speed

transfer rate

baud rate

(Following unit in page1-3, 13-3, 13-4, 13-14, 13-15, 13-24,

13-36, 13-46, 13-47.)

bps

• Conversion accuracy 10 bits ±4 LSB (Linearity error)

[Note 2]

When pin Nos. 48 to 45, respectively, are ...

(In the table 16-6-1.) Flash on-board write control register

(Name of FAREG in the table 16-6-1.) Flash address register

(

Name of FAREGEX in the table 16-6-1.

) Flash address register

(In the table 16-6-1.) Flash on-board write enable register

(From the 3rd line of [Ordering method 1].)

... for the user NMI processing routine. This is not necessary if NMIs

are not being used, however.)

(The 4th line of [Ordering method 2].)

...when an NMI ...

(The 6th line of [Ordering method 2].)

... of the user NMI processing routine ...

(The 7th line of [Ordering method 2].)

If the user is not using NMI processing, ...

(In the fig.17-2-2.) the NMI processing routine

P.12-5

P.12-7

P.12-8

P.13-43

Chapter

P.14-3

P.15-47

P.16-8

P.17-2

P.17-3

Appendix-

P.12-5

P.12-7

P.12-8

P.13-43

Chapter

P.14-3

P.15-47

P.16-8

P.17-2

P.17-3

Appendix-

- vii -

Overflow cycle

When CKSEL is "H" and oscillation frequency is 15 MHz

(or when CKSEL is "L" and oscillating frequency is 30 MHz)

Overflow cycle

When CKSEL is "H" and oscillation frequency is 15 MHz

75316420

SC3

TXF

SC3

RXF

SC3

TBF

SC3

RBF

SC3

CTS

SC3

FEF

SC3

PEF

SC3

OEF

Bit

name

Bit No.

Access

Reset

*1 Indicates the status of the external pin IRQ7

75316420

SC3

TXF

SC3

RXF

SC3

TBF

SC3

RBF

SC3

CTS

SC3

FEF

SC3

PEF

SC3

OEF

Bit

name

Bit No.

Access

Reset

PUTCX

PUTX

Dm D0

GETCHX

GETX

GETCLX

D0 2 2MCST

MCST9 Dm Dn

Dn D0 2 2

Source Destination

Code length

Format

Execution Cycle