2-16
CPU
LV2 to LV0 (Interrupt Priority Level) R/W
•This 3-bit field sets the interrupt priority level. When the interrupt priority level set in LV2 to LV0
is higher than the interrupt mask level set in IM2 to IM0 in the PSW (i.e., the value set in LV2 to
LV0 is smaller than the value set in IM2 to IM0), interrupts in the corresponding interrupt group
are enabled. All interrupts (max. 4) in the same interrupt group have the interrupt priority level
specified by LV2 to LV0.
•When interrupt requests are asserted simultaneously from multiple interrupt groups, the group with
the highest interrupt priority level is accepted. Also, when multiple interrupt groups are set to the
same interrupt priority level, the interrupt from the group with the highest priority ranking (the
interrupt group with the smallest group number) is accepted.
•All bits are cleared to "0" when the system is reset.
IE3 to IE0 (Interrupt Enable) R/W
•This field has up to 4 bits which specify interrupt approval. The IE3 to IE0 bits correspond to each
interrupt factor (max. 4) in the interrupt group. Interrupts are enabled when the corresponding IE3
to IE0 bit is "1".
•Interrupt occurs when IR3 to IR0 and IE3 to IE0 are set.
•All bits are cleared to "0" when the system is reset.
IR3 to IR0 (Interrupt Request) R/W
•This field has up to 4 bits which register interrupt requests. The IR3 to IR0 bits correspond to each
interrupt. After the interrupts are accepted, IR3 to IR0 should be cleared by the software during the
interrupt handler.
•All bits are cleared to "0" when the system is reset.
•Conditions for setting and clearing IR3 to IR0 are listed below.
ID3 to ID0 (Interrupt Detect) R/W
•This field has up to 4 bits which contain the logical product of IE3 to IE0 and IR3 to IR0. When an
interrupt allowed by IE3 to IE0 occurs, the bit corresponding to that interrupt goes to "1". This field
is used to specify interrupts within groups during interrupt processing.
•Interrupt requests are canceled by writing the specified values in IR3 to IR0 and ID3 to ID0 and
clearing the interrupt request field.
ID change (G0ICR) IR change (GnICR: n = 2 to 19)
Write ID after write
ID
0 Unchanged
10
Write IR after write
IR ID
0 0 Unchanged
01 0
1 0 Unchanged
11 1