Panasonic MN103001G/F01K

Extension Instruction Specifications

3-4

Multiply Register

Multiply & Accumulate

Overflow Detect Flag Register Bit 0

MCVF

Bit 31 Bit 0

MDRQ

MCRH

MCRL

3.2.2 Extension Block Register Set

The extension block has the following dedicated registers in which it stores the results of high-speed multiplication

operations and multiply-and-accumulate operations.

Fig. 3-2-1 Extension Block Register Set

■Multiply register (32 bits x 1 register)

This register is provided for high-speed multiplication instructions. A multiplication instruction uses this

■Multiply-and-accumulate register (higher) (32 bits x 1 register)

This register is provided for multiply-and-accumulate operation instructions. A multiply-and-accumulate

operation instruction uses this register to store the high-order 32 bits of the 64-bit multiply-and-accumulate

operation result.

■Multiply-and-accumulate register (lower) (32 bits x 1 register)

This register is provided for multiply-and-accumulate operation instructions. A multiply-and-accumulate

operation instruction uses this register to store the low-order 32 bits of the 64-bit multiply-and-accumulate

operation result.

■Multiply-and-accumulate overflow detect flag register (1 bit x 1 register)

This one-bit register is set when an overflow occurs in a multiply-and-accumulate operation. This flag is

not cleared until the next CLRMAC instruction or PUTCX instruction is executed.