Philips CBTD3306 , ,

Philips Semiconductors Product data

CBTD3306Dual bus switch with level shifting

2001 Nov 08 853-2305 27313

FEATURES

•Designed to be used in 5 V to 3.3 V level shifting applications with

internal diode.

•5 Ω switch connection between two ports

•TTL-compatible input levels

•Package options include plastic small outline (SO) and

thin shrink small outline (TSSOP)

•Latch-up protection exceeds 100 mA per JESD78

•ESD protection exceeds 2000 V HBM per JESD22-A114 and

1000 V CDM per JESD22-C101

DESCRIPTION

The CBTD3306 Dual FET Bus Switch features independent line

switches. Each switch is disabled with the associated Output Enable

(OE) input is high.

The CBTD3306 is characterized for operation from –40 to +85 °C.

PIN CONFIGURATION

1OE

GND

VCC

2OE

SA00535

PIN DESCRIPTION

PIN NUMBER SYMBOL NAME AND FUNCTION

1, 7 1OE, 2OE Output enable

2, 5 1A, 2A A port inputs

3, 6 1B, 2B B port outputs

4 GND Ground (0V)

8 VCC Positive supply voltage

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS

Tamb = 25 °C; GND = 0 V TYPICAL UNIT

tPLH

tPHL

Propagation delay

A to B or B to A CL = 50 pF; VCC = +5.0 V ±0.5 V 0.25 (MAX) ns

CIO(OFF) Pin capacitance (OFF state) VO = 3 V or 0; OE = VCC 6.50 pF

ICC Quiescent supply current VCC = 5.5 V; IO = 0, VI = VCC or GND 3µA

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE ORDER CODE DWG NUMBER

8-pin plastic SO –40 to 85 °C CBTD3306D SOT96-1

8-pin plastic TSSOP –40 to 85 °C CBTD3306PW SOT530-1

Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.

LOGIC DIAGRAM (positive logic)

1A 31B

SA00534

1OE

2A 62B

2OE

FUNCTION TABLE

INPUT

FUNCTION

LA port = B port

H Disconnect