Rev. 1.00, 05/04, page 534 of 544
SCK1, ExSCK1
t
SCKW
t
SCKr
t
SCKf
t
Scyc
Figure 22.17 SCK Clock Input Timing
TxD1, ExTxD1
(transmit data)
RxD1, ExRxD1
(receive data)
SCK1, ExSCK1
t
RXS
t
RXH
t
TXD
Figure 22.18 SCI Input/Output Timing (Synchronous Mode)
φ
ADTRG
t
TRGS
Figure 22.19 A/D Converter External Trigger Input Timing
t
RESOW
t
RESD
t
RESD
φ
RESO
Figure 22.20 WDT Output Timing (RESO)