Renesas 16-bit single-chip microcomputer, M16C/6NL, M16C/6NN - page 306

Rev.1.02 Jul 01, 2005 page 290 of 314
REJ09B0126-0102
M16C/6N Group (M16C/6NL, M16C/6NN) 22. Usage Precaution
Under development
This document is under development and its contents are subject to change.
22.9.1.4 Timer A (Pulse Width Modulation Mode)
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR
(i = 0 to 4) register, the TAi register, the TA0TGL and TA0TGH bits in the ONSF register and the TRGSR
register before setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register, the TA0TGL and TA0TGH bits in the ONSF register and the
TRGSR register are modified while the TAiS bit remains “0” (count stops) regardless whether after reset
or not.
The IR bit is set to “1” when setting a timer operation mode with any of the following procedures:
• Select the pulse width modulation mode after reset.
•Change an operation mode from timer mode to pulse width modulation mode.
•Change an operation mode from event counter mode to pulse width modulation mode.
To use the Timer Ai interrupt (the IR bit), set the IR bit to “0” by program after the above listed changes
have been made.
When setting TAiS bit to “0” (count stop) during PWM pulse output, the following action occurs:
• Stop counting.
• When TAiOUT pin is output “H”, output level is set to “L” and the IR bit is set to “1”.
• When TAiOUT pin is output “L”, both output level and the IR bit remain unchanged.
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If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-
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phase output forcible cutoff by input on NMI pin enabled), the TA1OUT, TA2OUT and TA4OUT pins go
to a high-impedance state.