Renesas HD6417641, SH7641 - page 13

Rev. 4.00 Sep. 14, 2005 Page xiii of l
Contents
Section 1 Overview................................................................................................1
1.1 Features..................................................................................................................................1
1.2 Block Diagram.......................................................................................................................7
1.3 Pin Assignments.....................................................................................................................8
1.4 Pin functions.......................................................................................................................... 9
Section 2 CPU......................................................................................................25
2.1 Registers...............................................................................................................................25
2.1.1 General Registers....................................................................................................29
2.1.2 Control Registers.................................................................................................... 31
2.1.3 System Registers.....................................................................................................35
2.1.4 DSP Registers......................................................................................................... 35
2.2 Data Formats........................................................................................................................42
2.2.1 Register Data Format (Non-DSP Type)..................................................................42
2.2.2 DSP-Type Data Formats.........................................................................................42
2.2.3 Memory Data Formats............................................................................................ 44
2.3 Features of CPU Core Instructions...................................................................................... 44
2.4 Instruction Formats.............................................................................................................. 48
2.4.1 CPU Instruction Addressing Modes....................................................................... 48
2.4.2 DSP Data Addressing............................................................................................. 51
2.4.3 CPU Instruction Formats........................................................................................ 58
2.4.4 DSP Instruction Formats.........................................................................................61
2.5 Instruction Set...................................................................................................................... 67
2.5.1 CPU Instruction Set................................................................................................ 67
2.6 DSP Extended-Function Instructions...................................................................................81
2.6.1 Introduction.............................................................................................................81
2.6.2 Added CPU System Control Instructions............................................................... 82
2.6.3 Single and Double Data Transfer for DSP Data Instructions..................................84
2.6.4 DSP Operation Instruction Set................................................................................88
Section 3 DSP Operation.....................................................................................99
3.1 Data Operations of DSP Unit...............................................................................................99
3.1.1 ALU Fixed-Point Operations..................................................................................99
3.1.2 ALU Integer Operations....................................................................................... 104
3.1.3 ALU Logical Operations.......................................................................................105
3.1.4 Fixed-Point Multiply Operation............................................................................107