Rev. 4.00 Sep. 14, 2005 Page xxx of l
Figure 3.14 Data Transfer Operation Flow.................................................................................119
Figure 3.15 Single Data-Transfer Operation Flow (Word).........................................................120
Figure 3.16 Single Data-Transfer Operation Flow (Longword).................................................121
Figure 3.17 Local Data Move Instruction Flow..........................................................................122
Figure 3.18 Restriction of Interrupt Acceptance in Repeat Loop............................................... 128
Figure 3.19 DSP Addressing Instructions for MOVX.W and MOVY.W...................................134
Figure 3.20 DSP Addressing Instructions for MOVS................................................................ 135
Figure 3.21 Modulo Addressing.................................................................................................136
Figure 3.22 Load/Store Control for X and Y Data-Transfer Instructions...................................140
Figure 3.23 Load/Store Control for Single-Data Transfer Instruction........................................141
Section 4 Clock Pulse Generator (CPG)
Figure 4.1 Block Diagram of Clock Pulse Generator.................................................................144
Figure 4.2 Note on Using a Crystal Resonator........................................................................... 152
Figure 4.3 Note on Using a PLL Oscillator Circuit.................................................................... 153
Section 5 Watchdog Timer (WDT)
Figure 5.1 Block Diagram of the WDT......................................................................................156
Figure 5.2 Writing to WTCNT and WTCSR..............................................................................159
Section 6 Power-Down Modes
Figure 6.1 Canceling Standby Mode with STBCR.STBY..........................................................173
Figure 6.2 STATUS Output at Manual Reset.............................................................................175
Figure 6.3 STATUS Output when Standby Mode is Canceled by an Interrupt..........................175
Figure 6.4 STATUS Output When Software Standby Mode is Canceled by a Manual Reset....176
Figure 6.5 STATUS Output when Sleep Mode is Canceled by an Interrupt..............................176
Figure 6.6 STATUS Output When Sleep Mode is Canceled by a Manual Reset.......................177
Section 7 Cache
Figure 7.1 Cache Structure......................................................................................................... 180
Figure 7.2 Cache Search Scheme............................................................................................... 187
Figure 7.3 Write-Back Buffer Configuration..............................................................................189
Figure 7.4 Specifying Address and Data for Memory-Mapped Cache Access.......................... 191
Section 8 X/Y Memory
Figure 8.1 X/Y Memory Address Mapping................................................................................194
Section 9 Exception Handling
Figure 9.1 Register Bit Configuration........................................................................................ 198
Section 10 Interrupt Controller (INTC)
Figure 10.1 Block Diagram of INTC..........................................................................................220
Figure 10.2 Interrupt Operation Flowchart.................................................................................239