Rev. 5.00, 09/03, page 69 of 760
3.4 MMU Functions
3.4.1 MMU Hardware Management
There are two k inds of MMU hardware management as follows:
1. The MMU decodes the virtual address accessed by a process and performs address translation
by controlling the TLB in accordance w ith the MMUCR settings.
2. In address translation, the MMU receives page management information from the TLB, and
determines the MMU exception and whether the cache is to be accessed (using the C bit). For
details of the determination method and the hardware processing, see section 3.5, MMU
Exceptions.
3.4.2 MMU Software Management
There are three kinds of MMU software management, as follows.
1. MMU register setting. MMUCR setting, in particular, should be performed in areas P1 and P2
for which address translation is not performed. Also, since SV and IX bit changes constitute
address trans l ation syst em ch anges , in this cas e, TLB flushing should be perfor med by
simultaneously writing 1 to the TF bit also. Since MMU exceptions are not generated in the
MMU disabled state with the AT bit cleared to 0, use in the disabled state must be avoided
with software that does not use the MMU.
2. TLB entry recording, deletion, and reading. TLB entry recording can be done in two ways by
using the LDTLB instruction, or by writing directly to the memory-mapped TLB. For TLB
entry deletion and reading, the memory allocation TLB can be accessed. See section 3.4.3,
MMU Instruction (LDTLB), for d e tails of the LDTLB instruct ion, and section 3.6,
Config u rat i on of Memory-Mapped TLB, for details of th e memory-m apped TLB.
3. MMU exception processing. When an MMU exception is generated, it is handled on the basis
of information set from the hardware side. See section 3.5, MMU Exceptio ns, for details.
When single virtual memory mode is used, it is possible to create a state in which physical
memory access is en abled in the privileged mode only by clearing the share status bit (SH) to 0 to
specify recording of all TLB entries. This strengthens inter-process memory protection, and
enables special access levels to be crea ted in the privileged mode only.
Recording a 1-kbyte page TLB entry may result in a synonym problem. See section 3.4.4,
Avoidi ng Synonym Probl ems.