Rev. 5.00, 09/03, page 122 of 760
Interrupts IRQ4–IRQ0 can wake the chip up from the standby state when the relevant interrupt
level is higher than the setting of I3–I0 in the SR register (but only when the RTC 32-kHz
oscillator is used).
If the IRQ edge is input immediately before the CPU enters the standby mode (during the period
between when th e CPU execut es a SL EEP instruction and w hen S TATUS0 becomes high level),
the interrupt may not be detected. However, the interrupt will be accepted correctly if the IRQ
edge i s re-input a ft er t he CPU has entered t he sta ndby mode (when STATUS0 i s high leve l ). In
addition, the interrupt may not be detected if the IRQ edge is input dur ing f r equency cha ng e
processing (WDT count).
6.2.3 IRL In terru pts
IRL interrupts are input by level at pins IRL3–IRL0 and IRLS3–IRLS0. IRLS3–IRLS0 are
enabled when the IRQLVL bit and IRLSEN bit in interrupt control register 1 (ICR1 ) are both 1.
The priority level is the higher level indicated by pins IRL3–IRL0 and IRLS3–IRLS0. An IRL3–
IRL0/IRLS3–IRLS0 value of 0 (0000) indicates the highest-level interru pt request (interru pt
priority level 15). A value of 15 (1111) indicates no interrupt request (interrupt priority level 0).
Figure 6.2 shows an example of IRL interrupt connection. Table 6.3 shows IRL/IRLS pins an d
interrupt levels.
Interrupt
request
Priority
encoder IRL3 to IRL0
4
SH7709S
IRL3 to IRL0
Interrupt
request
Priority
encoder IRLS3 to IRLS0
4IRLS3 to IRLS0
Figure 6.2 Example of IRL Interrupt Con n ect ion