Rev. 5.00, 09/03, page 171 of 760
3. When the condition is specified to be occurred after execu tion, the instructi o n se t with the
break condition is executed and then the break is generated prior to the execution of the next
instruction. As with pre-execution breaks, this cannot be used with overrun fetch instructions.
When t hi s ki nd of break is s et for a d elay b ranch instructio n, the bre a k is gen erated at t he
instruction that then first accepts the break.
4. When an instruction fetch cycle is set for channel B, break data register B (BDRB) is ignored.
There is thus no need to set break data for the break of the instruction fetch cycle.
7.3.3 Break by Data Access Cycle
1. The memory cyc l es in which CPU data access breaks occur are fr om instructions.
2. The relationship between the data acces s cycle address and the comparison condition for
operand size are listed in table 7.2:
Table 7.2 Data Access Cycle Addresses and Operand Size Comparison Conditions
Access Size Address Compared
Longword Compares break address register bits 31–2 to address bus bits 31–2
Word Compares break address register bits 31–1 to address bus bits 31–1
Byte Compares break address register bits 31–0 to address bus bits 31–0
This means that when address H'00001003 is set w ithout speci fying th e size con dition, for
example, the bus cycle in which the break condition is satisfied is as foll ows (where other
conditions are met).
Longword access at H'00001000
Word access at H'00001002
Byte access at H'00001003
3. When the data value is included in the break conditions on B channel:
When the data value is included in the break conditio ns, either longword, word, or byte is
specified as the operand size of the break bus cycle registers (BBRA and BBRB). When data
valu es are in cluded in break conditions , a break is generated when the address conditions and
data conditions both match. To specify byte data for this ca se, set the same data in two bytes at
bits 15–8 and bits 7–0 of the break data register B (BDRB) and break data mask register B
(BD M RB). When word or byte is s et, bits 31–16 of BDRB and BDM R B are ign ore d.
4. When the DMAC data access is included in the break condition:
When the address is included in the break condition on DMAC data access, the operand size of
the break bus cycle registers (BBRA and BBRB) should be byte, word or no specified operand
size. When the data value is included, select either byte or word.