Rev. 5.00, 09/03, page 215 of 760
9.7 WDT Registers
9.7.1 Watchdog Timer Counter (WTCNT)
The watchdog timer counter (WTCNT) is an 8-bit readable/writable counter that increments on the
selected clock. WTCNT differs from other registers in that it is more difficult to write to. See
section 9.7.3, Notes on Register Access, for details. When an overflow occurs, it generates a reset
in watchdog timer mode and an interrupt in interval time mode. Its address is H'FFFFFF84. The
WTCNT c ounter is initialize d to H'00 on ly by a power-on r e set through the RESETP pin. Use
word access to write to the WTCNT counter, with H'5A in the upper byte. Use byte access to read
WTCNT.
Bit:76543210
Initial value:00000000
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
9.7.2 Watchdog Timer Control/Status Register (WTCSR)
The watchdog ti mer control/status re gister ( WTCSR) is an 8-bit readable/writable register
composed of bits to select the clock used for the cou nt, bits to select the timer mode, and overflow
flags. WTCSR differs from other registers in that it is more difficult to write to. See section 9.7.3,
Notes on Register Access, for details. Its address is H'FFFFFF86. The WTCSR register is
initialized to H'00 only by a power-on reset through the RESETP pin. When a WDT overflow
causes an internal reset, WTCSR retains i ts value. When u sed to count the clock settling time for
canceling a standby, it retains its value after counter overflow. Use word access to write to the
WTCSR counter, with H'A5 in the upper byte. Use byte access to read WTCSR.
Bit:76543210
TME WT/IT RSTS WOVF IOVF CKS2 CKS1 CKS0
Initial value:00000000
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit 7—Timer Enable (TME): Starts and stops timer operation. Clear this bit to 0 when using the
WDT in standby mode or when changing the clock frequency.
Bit 7: TME Description
0 Timer disab led: Count-up stops an d WTCNT v alue is retai ned
(Initial value)
1 Timer enabled