Rev. 5.00, 09/03, page 253 of 760
10.2.8 Refresh Timer Control/Status Register (RTCSR)
The refresh timer control/status register (RTCSR) is a 16-bit readable/writable register that
spec ifie s the refresh cycle, whether to gene rate an interrup t, and th e cyc le of tha t in terrupt. It is
initialized to H'0000 by a p ower-on reset, but is not initialized by a manual reset or in standby
mode. Make the RTCOR setting before setting bits CKS2 to CKS0 in RTCSR.
Note: The met ho d of writing to RTCSR differ s f rom that for gener al regist e rs t o ensur e that
RTCSR is not r ewritten incorrectly. Use a word tr ans fer instruction to set the uppe r byte as
B'10100101 and the lower byte as the write data. For details, see section 10.2.12, Cautions
on A ccess ing R ef resh Control Relat e d Registers.
Bit: 15 14 13 12 11 10 9 8
————————
Initial value:00000000
R/W:RRRRRRRR
Bit:76543210
CMF CMIE CKS2 CKS1 CKS0 OVF OVIE LMTS
Initial value:00000000
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bits 15 to 8—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 7—Compare Ma tch Flag (CMF): Indicates that the values of RTCNT and RTCOR match.
Bit 7: CMF Description
0 The values of RTCNT and RTCOR do not match (Initial value)
Clearing condition: When a refresh is performed after 0 has been written to
CMF and RFSH = 1 and RMODE = 0 (to perform a CBR refresh)
1 The values of RTCNT and RTCOR match
Setting condition: RTC NT = RTCOR*
Note: * Contents do not change when 1 is written to C MF.
Bit 6—Compare Match Interrupt Enable (CM IE): Enables or disabl es an interrupt request
caused w hen CMF in RTCSR is se t to 1. Do not set this bit to 1 when using auto-refresh.
Bit 6: CMIE Description
0 Interrupt request by CMF is disabled (Initial value)
1 Interrupt request by CMF is enabled