Rev. 5.00, 09/03, page 264 of 760
Table 10.12 8-Bit External Device/Little-Endian Access and Data Alignment
Data Bus Strobe Signals
Operation D31–
D24 D23–
D16 D15–D8 D7–D0
W
WW
WE
EE
E3
33
3,
DQMUU
W
WW
WE
EE
E2
22
2,
DQMUL
W
WW
WE
EE
E1
11
1,
DQMLU
W
WW
WE
EE
E0
00
0,
DQMLL
Byte access at 0 — — — Data
7–0
Asserted
Byte access at 1 — — — Data
7–0
Asserted
Byte access at 2 — — — Data
7–0 Asserted
Byte access at 3 — — — Data
7–0 Asserted
Word acces s
at 0
1st time
at 0
———Data
7–0
Asserted
2nd time
at 1
———Data
15–8
Asserted
Word acces s
at 2 1st time
at 2 ———Data
7–0 Asserted
2nd time
at 3 ———Data
15–8 Asserted
Longword
acce ss at 0
1st time
at 0
———Data
7–0
Asserted
2nd time
at 1
———Data
15–8
Asserted
3rd time
at 2 ———Data
23–16 Asserted
4th time
at 3 ———Data
31–24 Asserted