Rev. 5.00, 09/03, page xxxvi of xliv
Figure 19.8 Port H................................................................................................................... 601
Figure 19.9 Port J .................................................................................................................... 603
Figure 19.10 Port K ................................................................................................................... 605
Figure 19.11 Port L.................................................................................................................... 607
Figure 19.12 SC Port ................................................................................................................. 609
Figure 20.1 Block Diagram of A/D Converter ........................................................................ 614
Figure 20.2 A/D Data Register Access Operation (Reading H'AA40).................................... 622
Figure 20.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) ......... 624
Figure 20.4 Example of A/D Co nverter Operation (Multi Mode, Channels AN0 to AN2
Selected)............................................................................................................... 626
Figure 20.5 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2
Selected)............................................................................................................... 628
Figure 20.6 A/D Conversion Timing....................................................................................... 629
Figure 20.7 External Trigger Input Timing ............................................................................. 630
Figure 20.8 Definitions of A/D Conversion Accuracy ............................................................ 632
Figure 20.9 Example of Analog Input Protection Circuit........................................................ 633
Figure 20.10 Analog Input Pin Equ ivalent Circui t .................................................................... 633
Figure 21.1 Block Diagram of D/A Converter ........................................................................ 635
Figure 21.2 Example of D/A Converter Operation.................................................................. 639
Figure 22.1 Block Diagram of UDI......................................................................................... 642
Figure 22.2 TAP Controller State Transitions......................................................................... 651
Figure 22.3 UDI Reset............................................................................................................. 653
Figure 23.1 EXTAL Clock Input Timing ................................................................................ 665
Figure 23.2 CKIO Clock Input Timing ................................................................................... 665
Figure 23.3 CKIO Clock Output Timing................................................................................. 665
Figure 23.4 Power-on Oscillation Settling Time ..................................................................... 666
Figure 23.5 Oscillation Settling Tim e at Standby Return (Return by Reset)........................... 666
Figure 23.6 Oscillation Settling Tim e at Standby Return (Retu r n by NMI)............................ 667
Figure 23.7 Oscillation Settling Time at Standby Return (Retu r n by IRQ4 to IRQ0,
PINT0/1, IRL3 to IRL0)....................................................................................... 667
Figure 23.8 PLL Synchronization Settling Time during Standby Recovery (Reset or NMI).. 668
Figure 23.9 PLL Synchronization Settling Tim e during Standby Recovery (IRQ/IRL or
PINT0/PINT1 Interrupt)....................................................................................... 668
Figure 23.10 PLL Synchronization Settling Time when Frequency Multiplication Rate
Modified............................................................................................................... 669
Figure 23.11 Reset Input Timing............................................................................................... 671
Figure 23.12 Interrupt Signal Input Timing............................................................................... 671
Figure 23.13 IRQOUT Timing.................................................................................................. 671
Figure 23.14 Bus Release Timing.............................................................................................. 672
Figure 23.15 Pin Drive Timing at Standby................................................................................ 672
Figure 23.16 Basic Bus Cycle (No Wait) .................................................................................. 675
Figure 23.17 Basic Bus Cycle (One Wait)................................................................................. 676
Figure 23.18 Basic Bus Cycle (External Wait, WAITSEL = 1)................................................ 677