Rev. 5.00, 09/03, page 500 of 760
Table 15.7 Maximum Bit Rates for Frequencies (Smart Card Interface Mode)
Pφ
φφ
φ (MHz) Maximum Bit Rate (Bits/s) N n
7.1424 9600 0 0
10.00 13441 0 0
10.7136 14400 0 0
13.00 17473 0 0
14.2848 19200 0 0
16.00 21505 0 0
18.00 24194 0 0
The bit rate error is found as follows:
Error (%) = ( × 10
6
− 1) × 100
1488 × 2
2n−1
× B × (N + 1)
Pφ
Table 15.8 shows the relationship between transmit/receive clock register set values and output
states on the smart card interface.
Table 15.8 Register Set Values and SCK Pin
Register Value SCK Pin
Setting SMIF C/A
AA
ACKE1 CKE0 Output State
1*11 0 0 0 Port Determined by setting of port
register SCP1MD1 and
SCP1MD0 bits
1001 SCK (serial clock) output state
2*21 1 0 0 Low output Low output state
1101 SCK (serial clock) output state
3*21 1 1 0 High output High output state
1111 SCK (serial clock) output state
Notes: 1. The SCK output state changes as soon as the CKE0 bit is modified. The CKE1 bit
should be cleared to 0.
2. The clock duty rem ain s con stant despite stopping and starting of t he clo ck by
modification of the CKE0 bit.