Rev. 5.00, 09/03, page 622 of 760
20.3 Bus Master Interface
ADDRA to ADDRD are 16-bit registers, but they are connected to the bus master by the upper 8
bits of the 16-bit peripheral data bus. Therefore, although the upper byte can be accessed directly
by the bus master, the lower byte is read through an 8-bit temporary register (TEMP).
An A/D data register is read as follows. When the upper byte is read, the upper-byte value is
transferred directly to the bus master and the lower-byte value is transferred into TEMP. Next,
when the lower byte is read, the TEMP contents are transferred to the bus master.
When reading an A/D data re gister, always read the upper byte before the lower byte. It is possible
to r e ad only the up p er byte, bu t if only the lower byte is r ead , the read value is not guaranteed.
Figure 20.2 shows the data flow for access to an A/D data register.
See section 20.7.3, Access Size and Read Data.
Bus
interface
TEMP
[H'40]
ADDRn L
[H'40]
ADDRn H
[H'AA]
CPU
(H'AA)
Upper byte read
Module internal data bus
Bus
interface
TEMP
[H'40]
ADDRn L
[H'40]
ADDRn H
[H'AA] n = A to D
CPU
(H'40)
Lower byte read
Module internal data bus
Figure 20.2 A/D Data Register Access Operation (Reading H'AA40)