Rev. 5.00, 09/03, page 26 of 760
2.3 Instruction Features
2.3.1 Execution Envi ronment
Data Length: The SH7709S ins t ruction s e t is impl em en t e d with fixed-length 16-bit wi de
instructions executed in a pipelined sequence with single-cycle execution for most instructions.
All operations are executed in 32-bit longword units. Memory can be accessed in 8-bit byte, 16-bit
word, or 32-bit longword units, with byte or word units sign-extended into 32-bit longwords.
Literals are sign-extended in arithmetic ope r ations (MOV, ADD, and CMP/EQ instructions) and
zero-extended in logical operations (TST, AND, OR, and XOR instructions).
Load/Store Architecture: The SH7709S features a load-store architecture in which basic
operations are executed in registers. Operations requiring memory access are executed in registers
following register loading, except for bit-manipulatio n oper atio ns such as logical AND functions,
which are executed directly in memory.
Delayed Branching: Unconditional br anching is imple mented as dela yed br anch operations.
Pip e line disruptions due to branching are minimized by the execution of the ins truct ion following
the dela yed branch ins truction p r ior t o br anching. C onditional branch instructions are of two
kinds, delayed and normal.
BRA TRGET
ADD R1, R0 ;ADD is executed prior to branching to TRGET