Rev. 5.00, 09/03, page 673 of 760
23.3.3 AC Bus Timing
Table 23.7 Bus Timing
Clock Modes 0/1/2/7, VccQ = 3.3 ± 0.3 V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3 V,
Ta = –20 to 75°C
Item Symbol Min Max Unit Figure
Address delay time tAD 1.5 12 ns 23.16–23.36, 23.39–23.46
Address setup time tAS 0 — ns 23.16–23.18
Address hold time*1tAH 4 — ns 23.16–23.21
BS delay time tBSD — 10 ns 23.16–23.36, 23.40–23.46
CS delay time 1 tCSD1 0 10 ns 23.16–23.21, 23.40–23.46
CS delay time 2 tCSD2 — 10 ns 23.16–23.21
CS delay time
(SDRAM access) tCSD3 1.5 10 ns 23.22–23.39
Read/write delay time tRWD 1.5 10 ns 23.16–23.46, 23.39–23.46
Read/write hold time tRWH 0 — ns 23.16–23.21
Read strobe delay time tRSD — 10 ns 23.16–23.21 23.40–23.43
Read data setup time 1 tRDS1 6 — ns 23.16–23.21, 23.40–23.46
Read data setup time 2 tRDS2 5 — ns 23.22–23.25, 23.30–23.33
Read data hold time 1*2tRDH1 0 — ns 23.16–23.21, 23.40–23.46
Read data hold time 2 tRDH2 1 — ns 23.22–23.25, 23.30–23.33
Write enable delay time tWED — 10 ns 23.16–23.18, 23.40, 23.41
Write data delay time 1 tWDD1 — 14 ns 23.16–23.18, 23.40, 23.41, 23.44–23.46
Write data delay time 2 tWDD2 1.5 12 ns 23.26–23.29, 23.34–23.36
Write data hold time 1 tWDH1 1.5 — ns 23.16–23.18, 23.40, 23.41, 23.44–23.46
Write data hold time 2 tWDH2 1.5 — ns 23.26–23.29, 23.34–23.36
Write data hold time 3 tWDH3 2 — ns 23.16–23.18
Write data hold time 4 tWDH4 2 — ns 23.40, 23. 41, 23.44–23 .46
WAIT setup time tWTS 5 — ns 23.17–23.21, 23.41, 23.43, 23.45, 23.46
WAIT hold time tWTH 0 — ns 23.17–23.21, 23.41, 23.43, 23.45, 23.46
RAS delay time 2 tRASD2 1.5 10 ns 23.22–23.39
CAS delay time 2 tCASD2 1.5 10 ns 23.22–23.39
DQM delay time tDQMD 1.5 10 ns 23.22–23.36
CKE delay time tCKED 1.5 10 ns 23.38