Rev. 5.00, 09/03, page 709 of 760
DRAK0/1
CKIO
t
DRAKD
t
DRAKD
Figure 23.54 DRAK Output Timing
23.3.9 UDI-Related Pin Timing
Table 23.9 UDI-Related Pin Timing
VccQ = 3.3 ± 0.3V, Vcc = 1.55 to 2.15 V, AVcc = 3.3 ± 0.3V, Ta = –20 to 75°C
Item Symbol Min Max Unit Figure
TCK cycle time tTCKCYC 50 —ns 23.55
TCK high pulse width tTCKH 12 —ns
TCK low pulse width tTCKL 12 —ns
TCK rise/fall time tTCKf —4ns
TRST setup time tTRSTS 12 —ns 23.56
TRST hold time tTRSTH 50 — tcyc
TDI setup time tTDIS 10 —ns 23.57
TDI hold time tTDIH 10 —ns
TMS setup time tTMSS 10 —ns
TMS hold time tTMSH 10 —ns
TDO delay time tTDOD —16 ns
ASEMD0 setup time tASEMDH 12 —ns 23.58
ASEMD0 hold time tASEMDS 12 —ns
t
TCKL
t
TCKf
V
IL
V
IL
V
IH
V
IH
V
IH
1/2
VccQ
1/2
VccQ
Note: When clock is input from TCK pin
t
TCKf
t
TCKH
t
TCKCYC
Figure 23.55 TCK Input Timing