3.5.3Thermal Head Electrical Characteristics (LTPF247)
Table
(Ta=25 ± 10°C)
Item |
| Symbol | Conditions |
| Rated value | Unit | |||
| MIN |
| TYP | MAX | |||||
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Head resistance | RH |
| 630.5 |
| 650 | 669.5 | Ω | ||
Head drive voltage | Vp |
| 21.6 |
| 24.0 | 26.4 | V | ||
Head drive current | Ip | At max. simultaneously | − |
| 9.2 | 10.4 | A | ||
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| activated dots |
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| number=248 |
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Logic block voltage | Vdd |
| 4.75 |
| 5.00 | 5.25 | V | ||
Logic block current | Idd | fCLK=8MHz,fDI=1/2fCLK | − |
| − | 64 | mA | ||
Input voltage |
| "High" | VIH | CLK,DAT,LATCH,DST | 0.8⋅Vdd |
| − | Vdd | V |
| "Low" | VIL | CLK,DAT,LATCH,DST | 0 |
| − | 0.2⋅Vdd | V | |
DAT input |
| "High" | IIH DAT | VIH = 5V | − |
| − | 0.5 | ∝A |
current |
| "Low" | IIL DAT | VIL = 0V | − |
| − | −0.5 | ∝A |
DST input |
| "High" | IIH DST |
| − |
| − | 120 | ∝A |
current |
| "Low" | IIL DST |
| − |
| − | −2.0 | ∝A |
CLK input |
| "High" | IIH CLK |
| − |
| − | 2.0 | ∝A |
current |
| "Low" | IIL CLK |
| − |
| − | −2.0 | ∝A |
LATCH input |
| "High" | IIH LAT |
| − |
| − | 2.0 | ∝A |
current |
| "Low" | IIL LAT |
| − |
| − | −2.0 | ∝A |
DAT output |
| "High" | VDOH | OPEN state, Vdd =4.5V | 4.45 |
| − | − | ∝A |
current |
| "Low" | VDOL |
| − |
| − | 0.05 | ∝A |
CLK frequency | f CLK |
| − |
| − | 4 | MHz | ||
CLK pulse width | tw CLK | See Timing Chart | 35 |
| − | − | ns | ||
DAT | tsetup DI | See Timing Chart | 30 |
| − | − | ns | ||
DAT hold time |
| thold DI | See Timing Chart | 10 |
| − | − | ns | |
DAT out delay time | td DO | See Timing Chart | − |
| − | 120 | ns | ||
LATCH pulse width | tw LAT | See Timing Chart | 100 |
| − | − | ns | ||
LATCH setup time | tsetup LAT | See Timing Chart | 200 |
| − | − | ns | ||
LATCH hold time | thold LAT | See Timing Chart | 50 |
| − | − | ns | ||
DST setup time | tsetup DST | See Timing Chart | 300 |
| − | − | ns | ||
Output delay time | tDo | See Timing Chart | − |
| − | 10 | ns |