Siemens ERTEC200 - page 79

7.5.1 LBU Read from ERTEC 200 with separate Read/Write line (LBU_RDY_N active low)
LBU_CS_R_N/
LBU_CS_M_N
LBU_RD_N
LBU_A(20:0)A/
LBU_SEG(1:0)/
LBU_BE(1:0)_N
LBU_RDY_N
LBU_D(15:0)
tCSRS
t
ARS
t
RRE
t
RDE tRTD t
RDH
t
RAH
t
RCSH
tRAP
t
RR
Figure 13: LBU-Read-Sequence with separate RD/WR line
Parameter Description Min Max
tCSRS chip select asserted to read pulse asserted delay 0 ns
tARS address valid to read pulse asserted setup time 0 ns
tRRE read pulse asserted to ready enabled delay 5 ns 12 ns
tRDE read pulse asserted to data enable delay 5 ns 12 ns
tRAP ready active pulse width 17 ns 23 ns
tRTD ready asserted to data valid delay 5 ns
tRCSH read pulse deasserted to chip select deasserted delay 0 ns
tRAH address valid to read pulse deasserted hold time 0 ns
tRDH data valid/enabled to read pulse deasserted hold time 0 ns 12 ns
tRR read recovery time 25 ns
Table 25: LBU Read access timing with seperate Read/Write line
Copyright © Siemens AG 2007. All rights reserved. 79 ERTEC 200 Manual
Technical data subject to change Version 1.1.0