User’s Manual
3.5.3.1 DRAM Clock/Drive ControlThis section can set the DRAM clock/driver timing.
| Item |
| Options |
|
| Description |
|
|
|
| By SPD |
|
|
|
|
|
|
| 100NHz | Set the | memory bus frequency | to operate at | |
| DRAM Clock |
| 133 MHz | ||||
|
| various | values for the proper | memory clock | |||
|
| 166 MHz | |||||
|
|
| setting |
|
| ||
|
|
| 200 MHz |
|
| ||
|
|
|
|
|
| ||
|
|
| 266 MHz |
|
|
| |
|
|
| Manual |
|
|
| |
| DRAM Timing |
| Auto By SPD | Set the memory timings for the said timings or | |||
|
| Turbo | DRAM Cycle Lengths of 2 or 2.5. |
| |||
|
|
|
| ||||
|
|
| Ultra |
|
|
| |
|
| 1.5 / 2 |
| This controls the time dealy passing before the | |||
| SDRAM CAS Latency | 2 / 3 |
| ||||
|
| SDRAM starts to carry out a read command after | |||||
| (DDR/DDR2) | 2.5 / 4 |
| ||||
|
| receiving it. |
| ||||
|
| 3 / 5 |
|
| |||
|
|
|
|
|
| ||
|
|
| Diabled | Enables to set the interleave mode of the SDRM | |||
|
|
| 2 Bank | ||||
| Bank Interleave |
| interface | which allows banks of SDRAM to | |||
|
| 4 Bank | |||||
|
|
| alternate their refresh and access cycles. | ||||
|
|
| 8 Bank | ||||
|
|
|
|
|
| ||
|
|
| 2T | This item sets the length of time taking to | |||
|
|
| precharge a row in the memory module before | ||||
| Precharge to Active(Trp) |
| 3T | a row being active and appears only when | |||
|
| 4T | DRAM timing is set at Manual. Longer values | ||||
|
|
| |||||
|
|
| 5T | are safer but probably not acting the best | |||
|
|
|
|
| performance. |
| |
|
|
| 5T, 6T, 7T, 8T | This item sets the length of time that a row | |||
|
|
| staying active fore precharging and appears only | ||||
| Active to Precharge(Tras) |
| 9T, 10T, 11T, 12T | ||||
|
| when DRAM timing is set at Manual. Longer | |||||
|
| 13T, 14T, 15T, 16T | |||||
|
|
| 17T, 18T, 19T, 20T | values are safer but probably not acting the best | |||
|
|
|
|
| performance. |
| |
|
|
| 8T, 9T, 10T, 11T, | This timing controls the length of the delay | |||
|
|
| 12T, 13T, 14T, 15T, | ||||
| Active to CMD(Trcd) |
| 16T, 17T, 18T, 19T, | between when a memory bank is activated to | |||
|
|
| 20T, 21T, 22T, 23T, | when a read/write command is sent to that bank. | |||
|
|
| 24T, 25T, 26T |
|
|
| |
|
|
| 12T | Set the REF to ACT/REF to REF timing. | |||
|
|
| 13T | ||||
REF to ACT/REF to REF(Trfc) |
| This field appears when DRAM Timing is set at | |||||
| 14T | ||||||
|
|
| Manual. |
|
| ||
|
|
| 15T |
|
| ||
|
|
|
|
|
| ||
|
|
| 2T | Set the minimum time interval between | |||
| ACT(0) to ACT(1) (TRRD) |
| 3T | successive ACTIVE commands to the different | |||
|
| 4T | banks. This field appears when DRAM Timing is | ||||
|
|
| |||||
|
|
| 5T | set at Manual. |
| ||
| Read to Precharge (Trtp) |
| 2T | Use this option to select Read | to Precharge | ||
|
| 3T | (Trtp) to set the timing by dram SPD. | ||||
|
|
| |||||
| Write to Read CMD (Twtr) |
| 2T / 3T | Use this option to select Write to Read CMD | |||
|
| 1T / 2T | (Twtr) to set the timing by dram SPD. | ||||
|
|
| |||||
|
|
| 2T |
|
|
| |
| Write Recovery Time (Twr) |
| 3T | Use this option to select Write Recovery Time | |||
|
| 4T | (Twr) to set the timing by dram SPD. | ||||
|
|
| |||||
|
|
| 5T |
|
|
| |
| DRAM Command Rate |
| 2T Command | Allows to set the DRAM Command Rate. | |||
|
| 1T Command | |||||
|
|
|
|
|
| ||
| RDSAIT mode |
| Manual |
|
|
| |
|
| Auto |
|
|
| ||
|
|
|
|
|
| ||
| RDSAIT selection | 3 |
| Key in a HEX number (Min = 0000, Max = 003F) |