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Redundancy CPU Considerations
The Redundancy CPU (CPU 780) has several restrictions and differences in operation as compared to other Series
HI/O Interrupts
HTimed Interrupts
HVME Integrator Racks.
HStop I/O Scan mode
HFlash operation
Features not Available with CPU 780
I/O Interrupts
I/O Interrupts are not supported by the Redundancy CPU (CPU 780). This includes the single edge triggered interrupts from the discrete input modules, the high alarm and low alarm interrupts from the analog input modules, and interrupts from foreign VME modules, all of which can be used to trigger a ladder diagram program block. In order to prevent I/O interrupts from changing the data being transferred from one CPU to another, interrupts would have to be disabled for the entire transfer time. Programs which declare I/O Interrupt triggers cannot be stored to the CPU 780 (the program will be rejected causing an abort of the store). In addition, any configuration containing an enabled I/O interrupt for a discrete or analog input module will cause a fatal system configuration mismatch fault.
Timed Interrupts
Timed Interrupts are not supported by the Redundancy CPU (CPU 780). Timed Interrupts would have the same interrupt latency problem as the I/O Interrupts. Programs which declare Timed Interrupt triggers cannot be stored.
VME Integrator Racks
The VME Integrator Racks (IC697CHS782 and IC697CHS783) that support half size modules are not supported with this release of the Hot Standby CPU Redundancy product.
STOP/IOSCAN Mode
TheSTOP/IOSCAN mode is not valid in a redundant system. If an attempt is made to place the PLC in this mode, the PLC will reject the selection and return an error. A message will be displayed on the programmer with this information.
Flash Operation
Flash memory operation is not supported in this release of the CPU 780.
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