Analog Devices ADuC812 SPI Slave Mode Timing Cpha =, SS to Sclock Edge, SS High after Sclock Edge

ADuC812

Parameter		Min	Typ	Max	Unit	Figure
SPI SLAVE MODE TIMING (CPHA = 1)
tSS	SS to SCLOCK Edge	0			ns	59
tSL	SCLOCK Low Pulsewidth		330		ns	59
tSH	SCLOCK High Pulsewidth		330		ns	59
tDAV	Data Output Valid after SCLOCK Edge			50	ns	59
tDSU	Data Input Setup Time before SCLOCK Edge	100			ns	59
tDHD	Data Input Hold Time after SCLOCK Edge	100			ns	59
tDF	Data Output Fall Time		10	25	ns	59
tDR	Data Output Rise Time		10	25	ns	59
tSR	SCLOCK Rise Time		10	25	ns	59
tSF	SCLOCK Fall Time		10	25	ns	59
tSFS	SS High after SCLOCK Edge	0			ns	59

SS

SCLOCK (CPOL=0)

SCLOCK (CPOL=1)

MISO

MOSI

tSS

tSH	tSL
tDAV	tDF
	MSB

MSB IN

tDR

BIT 6 – 1

BIT 6 – 1

tSFS

tSR tSF

LSB

LSB IN

tDSU tDHD

Figure 58. SPI Slave Mode Timing (CPHA = 1)

–54– REV. B